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83023am www.icst.com/products/hiperclocks.html rev. b february 4, 2002 1

ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary g eneral d escription the ics83023 is a dual, 1-to-1 differential- to-lvcmos fanout buffer and a member of the hiperclocks? family of high perfor- mance clock solutions from ics. the ics83023 has 2 differential clock input pairs. f eatures ? 2 lvcmos / lvttl outputs ? 2 differential clkx, nclkx input pairs ? clk, nclk pairs can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? output frequency: 350mhz (typical) ? output skew: 60ps (typical) ? part-to-part skew: 500ps (maximum) ? small 8 lead soic package saves board space ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? pin-to-pin compatible with mc100ept23 b lock d iagram p in a ssignment ics83023 8-lead soic 3.8mm x 4.8mm, x 1.47mm package body m package top view clk0 nclk0 nclk1 clk1 1 2 3 4 hiperclocks? v dd q0 q1 gnd 8 7 6 5 q0 clk0 nclk0 q1 clk1 nclk1 the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v 6 . 3 =f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? r t u o e c n a d e p m i t u p t u o 7 ? r e b m u ne m a ne p y tn o i t p i r c s e d 10 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 20 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 31 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 41 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 5d n gr e w o p. d n u o r g o t t c e n n o c . d n u o r g y l p p u s r e w o p 61 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e l g n i s 70 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e l g n i s 8v d d r e w o p. v 3 . 3 o t t c e n n o c . n i p y l p p u s e v i t i s o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 112.7 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in th e dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect product reliability. t able 3a. p ower s upply dc c haracteristics , v dd = 3.3v0.3v, t a = -40 c to 85 c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v dd egatlovylppusevitiso p0 . 33 . 36 . 3v i dd tnerrucylppusevitisop 1 1 a m t able 3b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v0.3v, t a = -40 c to 85 c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v ho 1eton;egatlovhgihtuptu o6 . 2v v lo 1eton;egatlovwoltuptuo 5. 0v 05htiwdetanimretstuptuo:1eton ? vot dd .tiucrictsetdaoltuptuov3.3,noitcestnemerusaemretemarapees.2/ t able 3c. d ifferential dc c haracteristics , v dd = 3.3v0.3v, t a = -40 c to 85 c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu i hi tnerruchgihtupni 1klcn,0klc nv ni v= dd v6.3 =5a 1klc,0kl cv ni v= dd v6.3 =0 5 1a i li tnerrucwoltupni 1klcn,0klc nv ni v,v0= dd v6.3 =0 51 -a 1klc,0kl cv ni v,v0= dd v6.3 =5 -a v pp egatlovtupnikaep-ot-kaep 51. 03 . 1v v rmc ;egatlovtupniedomnommoc 2,1eton 5.0+dn gv dd 58.0 -v snoitacilppadedne-elgnisrof:1eton , vsixklcn,xklcrofegatlovtupnimumixameht dd .v3.0+ siegatlovedomnommoc:2eto nv sadenifed hi .
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary t able 4. ac c haracteristics , v dd = 3.3v0.3v, t a = -40 c to 85 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 3z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p 8 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 6s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 5s p t r e m i t e s i r t u p t u ov 2 o t v 8 . 00 5 2s p t f e m i t l l a f t u p t u ov 2 o t v 8 . 00 5 2s p c d oe l c y c y t u d t u p t u o 0 5% f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u v o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n d d . t u p t u o e h t f o 2 / . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m d d . 2 / s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a v t a d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary scope qx lvcmos 3.3v o utput l oad t est c ircuit -1.65v0.15v gnd v dd 1.65v0.15v p arameter m easurement i nformation d ifferential i nput l evel v cmr cross points v pp nclk0, nclk1 clk0, clk1 gnd v dd
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary o utput s kew qx qy t sk(o) v dd 2 v dd 2 p art - to -p art s kew qx qy part 1 part 2 t sk(pp) v dd 2 v dd 2 i nput and o utput r ise and f all t ime clock inputs and outputs 0.8v 2v 2v 0.8v t r t f
83023am www.icst.com/products/hiperclocks.html rev. b february 4, 2002 7

ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary p ropagation d elay clk0, clk1 q0, q1 t pd v dd 2 nclk0, nclk1 t pw & t p eriod t pw t period v dd 2 v dd 2 v dd 2 t pw t period odc = q0, q1
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary t ransistor c ount the transistor count for ics83023 is: 416 t able 5. vs . a ir f low t able ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3 c/w 128.5 c/w 115.5 c/w multi-layer pcb, jedec standard test boards 112.7 c/w 103.3 c/w 97.1 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary t able 6. p ackage d imensions reference document: jedec publication 95, ms-012 p ackage o utline - s uffix m l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
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ics83023 d ual , 1- to -1 d ifferential - to -lvcmos f anout b uffer preliminary t able 7. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industiral applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t m a 3 2 0 3 8 s c im a 3 2 0 3 8c i o s d a e l 8e b u t r e p 6 9c 5 8 o t c 0 4 - m a 3 2 0 3 8 s c im a 3 2 0 3 8l e e r d n a e p a t n o c i o s d a e l 80 0 5 2c 5 8 o t c 0 4 -

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